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Popeye-T/README.md

  • systemverilog verilog markdown CSDN

  • Questasim vivado quartus lceda Gowin

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  1. Serial_port-Digital_tube Public

    串口上位机-FPGA数码管计数板，工程项目存档，计数频率可变（上位机控制）

    C++ 3

  2. PLL_ADC_Capture Public

    ZYNQ数据采集卡，工程项目存档：V1为USB传输方案，V2为ETH传输方案

    VHDL 3 2

  3. VideoCoding-Material Public

    视频编解码相关资料存档，FFmpeg、H264等等，后续更新管理

    HTML 1

  4. XAZU3EG-FZ3A Public

    海鲜市场600收了一块3EG，存个档

    C

  5. AXI_FULL_CTRL Public

    AXI4控制器，内含FIFO增强传输稳定性

    VHDL

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June 2025

Created 4 commits in 2 repositories
Created 2 repositories
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